This invention relates to processing of data information in error control encoding.
In parity-based error control procedures that are presently used, data representing a xe2x80x9cbarexe2x80x9d message, without error control bytes attached thereto, are read from memory three times: once to calculate an error detection control (EDC) segment, once to calculate a P-parity checkbyte, and once to calculate a Q-parity checkbyte for error correction control (ECC). Each read operation requires a certain time increment, and this triple reading of each data byte adds substantially to the total time required to generate error detection bytes and error correction bytes on a given data block.
What is needed is an approach that reduces to one the number of times a given array of data elements must be read from memory, without substantially increasing the time required for subsequent processing of the data for ECC encoding purposes. Preferably, the approach should be flexible enough to allow each data element received to be used for more than one computation and should not require that the error control procedures be performed in a particular order. Preferably, the approach should extend to data element arrays of arbitrary size.
These needs are met by the invention, which provides a modified procedure for using an array of data elements, each read once from memory, received separately at an EDC processor, at an ECC P-parity processor and at an ECC Q-parity processor, and processed in parallel in the three processors to compute an EDC error detection term and, simultaneously, to compute two ECC P-parity syndromes s0 and s1 and two ECC Q-parity syndromes. A first algorithm is used at the EDC processor to compute the EDC term by receiving the sequence {s(k)} of data elements (k=0, 1, . . . , Mxc2x7Nxe2x88x921, with M=24 and N=43 in an example) in serial order and computing the EDC terms as the data elements are received. A second algorithm is used in parallel at the ECC-P processor to compute components of two ECC P-parity syndromes (and, optionally, two corresponding ECC P-parity checkbytes) as the data elements are received in serial order. A third algorithm is used in parallel at the ECC-Q processor to compute components of two ECC Q-parity syndromes (and, optionally, two ECC Q-parity checkbytes) as the data elements are received in serial order. Because the three processors operate independently but in parallel, the time required for combined EDC, ECC-P and ECC-Q processing is about one-third of what would otherwise be required, and each data element value s(k) need only be read once from memory.